1. Field of the Invention
The invention relates to the field of metal-oxide-semiconductor (MOS) electrically programmable and electrically erasable read-only memories (EEPROMs) having floating gates and to electrically programmable read-only memories (EPROMs).
2. Prior Art
The most commonly used EPROM cell has an electrically floating gate which is completely surrounded by insulation and generally disposed between a source and drain region formed in a silicon substrate. In early versions of these cells, charge is injected through the insulation by avalanche injection such as the device described in U.S. Pat. No. 3,660,819. Later versions of EPROMs relied on channel injection for charging the floating gate as shown in U.S. Pat. Nos. 4,142,926; 4,114,255 and 4,412,310. These EPROMs are erased by exposing the array to ultraviolet radiation.
Electrically erasable EPROMs (EEPROMs) are also commercially available. In some cases, charge is placed into and removed from a floating gate by tunnelling the charge through a thin oxide region formed on the substrate (see U.S. Pat. No. 4,203,158). In other instances, charge is removed through an upper electrode (see U.S. Pat. No. 4,099,196).
More recently, a new category of electrically erasable EPROMs has emerged sometimes referred to as "flash" EPROMs or EEPROMs. In these memories, the entire array is simultaneously erased, electrically. The cells themselves use only a single device per cell and such cells are described in copending application, Ser. No. 892,446, filed Aug. 4, 1986, entitled "Low Voltage EEPROM Cell". The present invention is directed towards use of these cells.
EPROM memories most often removed from their printed circuit boards for both erasing and programming. A special programming device is used for programming the cells. This device verifies that the cells have been properly programmed by raising the V.sub.CC potential to approximately 6.25 volts for a "5 volt" memory. If "zeroes" can be read at 6.25 volts, it is then assumed that the zeroes will be able to be read over the life of the memory at a V.sub.CC potential of 5.5 volts. (This should be the highest voltage the memory encounters when properly used with a regulated 5 volt power supply.) During programming, electrons are transferred to the floating gate making the cells less conductive. If the application of the 6.25 volts to the control gate causes the cell to remain non-conductive during a read cycle, sufficient negative charge has been transferred to the floating gate so that the device will operate satisfactorily over its life.
EEPROMs are typically programmed and erased while installed in the same circuit (e.g., printed circuit board) used for reading data from the memory. That is, a special programming device is not needed. In some cases "on chip" circuits are used to verify that the programming has been properly performed.
Electrically erasing some floating gate device gives rise to another problem, specifically overerasing. Too much charge can be removed, making the device "depletion-like". Cells may require testing after being erased to verify that the floating gate is erased, but not too positively charged.
U.S. Pat. No. 4,460,982 disclosed an "intelligent" EEPROM which provides means for verifying both programming and erasing.
The closest prior art known to Applicant is an article entitled "A 256-k Bit Flash E.sup.2 PROM Using Triple-Polysilicon Technology" IEEE Journal Solid-State Circuits. Vol. SC-22, No. 4, August, 1987 and the above mentioned U.S. Pat. No. 4,460,982.